Senior Design-for-Test Engineer, ATPG – NVIDIA

Job Description

NVIDIA is hiring a DFT engineer to join the ATPG team and contribute to next-generation semiconductor technologies. The role focuses on developing DFT/ATPG flows, managing end-to-end ATPG activities, creating automation solutions, and supporting post-silicon validation. The position involves collaboration across chip design, backend, verification, and production testing teams while contributing to advanced and innovative hardware products.

Location: Tel Aviv, Israel

Qualification: BSc. in Electrical Engineering

Experience: 5+ years

Apply: Click Here

Responsibilities

• Design and implement cutting-edge ATPG flow for complex semiconductor chips.
• Manage the entire ATPG process, starting from planning to verification and validation.
• Drive improvements in DFT methodologies to support advanced chip architectures and testing requirements. 
• Implement automation flow to make sure the efficiency of the manufacturing test is maximized.
• Work closely with the chip design, backend, verification, and manufacturing test engineering team.

Requirements

• Minimum five to six years of experience in DFT/ATPG for ASIC design and ATPG tools.
• Proven ability in coding and scripting for engineering automation and development.
• BSc. in Electrical Engineering or Computer Engineering.
• Practical knowledge in DFT implementation techniques, ATPG methodology, and semiconductor testing.
• Proactive learning approach with a sense of ownership and commitment to engineering teams.

Preferred Qualifications

• Experience in scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
• Experience in Mentor Test Kompress ATPG tool and efficient retargeting flows.
• Programming experience in TCL, Perl, Python, and UNIX shell scripting environments.
• Experience with ATE environments, production tests, and semiconductor validation.
• Experience with silicon bring-up, post-silicon validation, diagnosis, and production readiness.