Silicon AI/ML DFT Engineer, TPU, Google Cloud, Google

DFT Engineer
Karnataka, India, Bengaluru
April 30, 2026
Full Time

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Job Description

Google is searching for a Silicon AI/ML DFT Engineer who will create and execute Design for Test DFT procedures which will be used to test upcoming TPU Tensor Processing Unit hardware. The position requires DFT architecture development which includes scan and MBIST insertion and SoC testing method creation and collaboration with hardware teams to enhance silicon quality and production efficiency and testing performance.

Qualification: Bachelor’s degree in Electrical Engineering or related field

Experience: 3+ years

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Main Duties

  • Define and document DFT architecture and test sequences including boot-up procedures and test pin configurations.
  • Perform DFT logic insertion such as Scan and BIST at RTL and netlist levels.
  • Execute DFT validation processes including scan coverage analysis and Memory Built-In Self Test (MBIST) verification.
  • Plan SoC and subsystem level DFT strategies and collaborate with design, verification, and physical design teams.
  • Develop DFT timing constraints and support Static Timing Analysis (STA) and physical design implementation.
  • Conduct quality checks such as Lint and CDC on DFT RTL modes and assist with silicon debug and verification activities.

Essential Qualifications

  • Bachelor’s degree in Electrical Engineering or a related technical field. 
  • Experience with Design for Test (DFT) technologies which include Scan and ATPG and MBIST. 
  • Knowledge of ASIC DFT synthesis and simulation and verification flows and STA processes. 
  • Experience in analog and mixed-signal integrated circuit design environments. 
  • Implement DFT logic and validate it within extensive SoC system architectures.

Preferred Skills

  • Master’s degree in Electrical Engineering or its equivalent degree program. 
  • Automatic Test Equipment (ATE) engineers to execute silicon bring-up and debug needs. 
  • Knowledge about complete SoC development processes which include post-silicon validation and debugging procedures. 
  • Experience with the integration of IP components which includes memory test controllers TAP interfaces and MBIST modules.
  • Knowledge about fault modeling techniques which semiconductor testing utilizes to enhance yield results.