Silicon Senior uArch/RTL Engineer, Google Cloud

Silicon Senior uArch/RTL Engineer
Karnataka, India, Bengaluru
March 24, 2026
Full Time

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Job Description

Google Cloud is hiring a Silicon Senior uArch/RTL Engineer in Bengaluru. Lead RTL Implementation and microarchitecture development for AI accelerators, driving performance, power, and scalability. Collaborate across teams to deliver production-ready silicon solutions. Ideal for experienced uArch/RTL Engineers with strong Python and ASIC/SoC expertise. Apply now for this full-time opportunity.

Qualification: Bachelor’s Degree or equivalent experience

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Main Duties

  • Own microarchitecture and implementation of complex IPs and subsystems for AI accelerators.
  • Take responsibility for RTL implementation, validation, and quality checks of modules.
  • Collaborate with architecture, verification, and physical design teams to deliver production-ready silicon.
  • Drive improvements in Power, Performance, and Area (PPA) metrics for hardware modules.
  • Participate in synthesis, timing closure, power analysis, and silicon bring-up activities.
  • Contribute to design methodologies, debugging, and code reviews across engineering teams.
  • Evaluate design trade-offs considering complexity, performance, and scalability requirements.

Essential Qualifications

  • Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science or related fields. 
  • 8+ years of experience in ASIC and SoC development through their work with Verilog and SystemVerilog. 
  • Advanced skills for designing microarchitecture, developing subsystems and IP components. 
  • Experience with ASIC verification plus synthesis and timing analysis and power analysis and design for testability. 
  • Delivered complex silicon projects within actual production settings. 
  • Strong skills in analytical thinking and collaborative work and problem-solving.

Preferred Qualifications

  • Programming experience through Python, C, C++ and Perl. 
  • Knowledge about SoC integration pipelines and complete chip design workflows. 
  • Processor systems which include accelerators, bus systems, NoC networks, and memory system designs. 
  • Methods which enhance both performance and energy efficiency in design processes. 
  • Professional experience which involves working on ML acceleration systems and hardware components used in data centers.